BrainScaleS

Overview

BrainScaleS is a family of neuromorphic systems that emulate spiking neurons with analog electronic circuits. Instead of calculating neuron equations with numbers, the circuits obey similar equations through the physics of transistors and capacitors. Voltages rise and fall in the circuits much as the membrane voltage of a nerve cell would, and the circuits are built to run much faster than biology, by a factor of hundreds to thousands depending on the generation.

This speed is the main attraction. A network can live through hours of biological time in seconds of wall-clock time, which makes it practical to study learning and plasticity, where slow processes need long runs. The cost is that analog circuits are not perfectly identical, so each chip needs calibration and models must tolerate some variation. For tabular work, BrainScaleS is a research platform for fast spiking and plasticity experiments, not a place to run tabular foundation models. See spiking neural networks for the model class.

What it is

BrainScaleS is a mixed-signal neuromorphic architecture developed at a German university in cooperation with European partners, mainly within a large brain research initiative. The name stands for Brain-inspired multiscale computation in neuromorphic hybrid systems. It has appeared in two main generations.

First generation: wafer-scale

The first generation used whole silicon wafers that were not cut into separate chips. Many small neuromorphic dies on a wafer were linked by post-processed wiring, so that the whole wafer behaved as one large system. One wafer module held on the order of two hundred thousand neurons and tens of millions of synapses, and ran about ten thousand times faster than biological time. Several wafer modules were assembled into a larger system for researchers.

Second generation: single chip with a plasticity processor

The second generation, often called BrainScaleS-2, is a single chip with:

• A few hundred analog neuron circuits (on the order of 512), based on an adaptive exponential integrate-and-fire model.
• A large array of synapse circuits (on the order of 130 thousand), each with a small weight and with sensors that measure spike correlations.
• A plasticity processing unit, which is an embedded general-purpose processor with vector instructions. It reads the sensors and rewrites weights and neuron parameters.
• Digital event routing and links to a host computer.
• A speedup of about one thousand over biological time.

Analogy: the neuron circuits are like a row of hourglasses. In an ordinary computer, you track the sand with a counter and update it every tick. In BrainScaleS, you build real hourglasses that fill up on their own, only much faster than the biological ones. The plasticity processor is the clerk who watches the hourglasses and adjusts their settings between runs.

What it is not

• It is not a purely digital chip. Parts of it are analog, and their exact behavior varies from chip to chip.
• It is not designed for mainstream deep learning workloads.
• It is not a large cluster. A single chip has hundreds of neurons, and scaling needs many chips.
• It is not real-time hardware in the biological sense. It is much faster, which affects how you connect it to the physical world.

Where it came from

The analog route to neuromorphic computing goes back to the late 1980s, when researchers began to build silicon circuits that mimic neurons using transistors operated in a regime where they behave like exponential devices. Over time, work at several groups moved from single neurons to networks and from simple models to richer ones.

The BrainScaleS line grew out of European projects on brain-inspired computing. Its distinct choice was to give up real-time operation in favor of acceleration, so that slow learning processes could be explored quickly. Key points:

• The first system used wafer-scale integration, an unusual technique in which the wafer is not diced. This gave a large number of neurons with high-speed communication on a single module.
• Experiments on that system studied network dynamics, learning rules and sampling-based computation.
• The second generation moved to a single, more compact chip, with a flexible embedded processor for plasticity and with a more accurate neuron model that supports richer dynamics.
• Software evolved from low-level configuration tools to a PyNN-style interface and a PyTorch-based interface for machine learning use.

The hybrid approach, called hybrid plasticity, mixes fast analog circuits for the neurons and for measuring correlations with a digital processor that implements flexible learning rules. A research paper in 2019 and later described this design and demonstrated learning tasks on the chip.

Sibling platforms include Intel Loihi, IBM TrueNorth and SpiNNaker. For the broader research view, see /model/research.

How it works

Step 1: describe the network

A researcher describes populations of neurons and the connections between them through a Python interface. The interface supports the PyNN style for general spiking models and a PyTorch-based style for machine learning, in which the chip acts as a layer inside a trainable network.

Step 2: calibrate the chip

Analog circuits drift and differ. Two neuron circuits that are meant to be identical will have slightly different time constants and thresholds because of tiny manufacturing differences. This is called fixed-pattern noise.

Calibration measures each circuit and sets digital correction values so that the circuits behave like the target model. It is done once and stored for reuse, with occasional refresh.

Analogy: a set of guitar strings that each need tuning before a concert. They will never be identical, but with tuning they play the same notes close enough.

Step 3: map the network onto neurons and synapses

Each model neuron is assigned to a physical circuit. Weights are set by a small digital value in each synapse circuit, typically a few bits, and by the sign of the synapse. Connections are formed by routing spike events between circuits.

Step 4: run the emulation

Input spikes are injected at the right times. The analog circuits integrate the incoming currents. When a neuron's voltage passes its threshold, a digital spike is generated and routed to its targets. Because circuit time constants are about a thousand times shorter than biological ones, a millisecond of model time passes in about a microsecond of wall time.

Step 5: measure correlations and update weights

Each synapse has analog sensors that accumulate how often pre- and post-synaptic spikes occur close together. The plasticity processor can read these sensors, combine them with other signals such as a reward, and write new weights. This supports spike-timing-dependent plasticity and many other learning rules.

Step 6: read out

Spike times and membrane voltages can be recorded. The host collects them and computes the result.

In-the-loop training

Because analog circuits deviate from ideal models, gradients computed in software may not match the hardware exactly. In-the-loop training handles this by running the forward pass on the chip, computing errors on a host, and using a software surrogate to estimate gradients that update the weights. The hardware's own imperfections are thus included in the loop and can be partly compensated.

Analogy: tune your instrument while playing in the real hall, not in the quiet practice room. The hall's echo is part of the sound, and you correct for it as you go.

Why acceleration is useful

• Slow learning rules need many repeated trials. At a thousand times speed, a day of biological experience takes under two minutes.
• Parameter sweeps that would take weeks run in hours.
• Long-lived processes such as development and homeostasis can be explored.

Why it uses little energy

• Analog circuits compute by physics, with no clock and no arithmetic units for each neuron update.
• Synapse and neuron memory sit with the circuit.
• Only digital events leave the neuron, which are short and cheap.

Key concepts and terms

A worked example

We will do two things. First, we will compute by hand how time scales between the model and the hardware. Second, we will sketch the code that a researcher might write to use the chip as a layer inside a trained network. The code is illustrative. Names differ between software releases, so check the current documentation before relying on any call.

Time scaling

Suppose the speedup is 1,000.

• A model experiment that lasts 10 seconds of biological time takes 10 milliseconds on the chip.
• A learning task that needs 10,000 trials of 100 ms each is 1,000 seconds of biological time. On the chip, it takes about 1 second.
• A neuron with a membrane time constant of 20 ms in the model has a time constant of 20 microseconds in the circuit.

Now consider the interface with the outside world. A camera that sends images at 30 frames per second is slow on this clock. The chip can process one frame in far less time than the frame interval. It will spend most of its time waiting for data. This is why the speedup helps for batch experiments but does not help when the input arrives in real time.

Mapping a classifier layer

Imagine a layer with 64 inputs and 10 output neurons.

• Weights: 64 times 10 equals 640 synapses, well under the 130 thousand available.
• Outputs: 10 neuron circuits out of about 512.
• Weight precision: a few bits per synapse, so trained weights must be quantized.

A layer of this size fits many times over, so several copies could run in parallel, or a larger layer could be used.

A sketch in Python

import torch
import torch.nn as nn

# Pseudocode style: a hybrid model where one layer runs on the chip.
class HybridNet(nn.Module):
    def __init__(self, chip_layer):
        super().__init__()
        self.pre = nn.Linear(16, 64)          # runs on the host
        self.chip = chip_layer                # wraps the analog layer
        self.post = nn.Linear(10, 3)          # runs on the host

    def forward(self, x):
        h = torch.relu(self.pre(x))
        spikes_or_rates = self.chip(h)        # forward on hardware
        return self.post(spikes_or_rates)

# Training loop sketch for in-the-loop training
# model = HybridNet(chip_layer)
# for x, y in data:
#     out = model(x)                          # hardware in the loop
#     loss = nn.functional.cross_entropy(out, y)
#     loss.backward()                         # gradient via software surrogate
#     optimizer.step()

The point of the sketch is the structure. The chip is one stage in a larger model. The gradient through the chip stage is estimated by a software model of it, while the forward pass uses the real hardware.

A tiny calibration idea

The idea of calibration can be shown in a few lines. Suppose each circuit has an unknown gain, and we want outputs equal to the target.

import numpy as np

rng = np.random.default_rng(1)
true_gain = rng.normal(1.0, 0.1, size=8)         # fixed-pattern noise
target = 1.0
trim = np.ones(8)                                 # digital correction

for _ in range(20):
    measured = true_gain * trim                   # "measure" each circuit
    trim *= target / measured                     # adjust the digital trim

print(np.round(true_gain * trim, 3))              # all close to 1.0

Real calibration is more complex, since many parameters interact, but the pattern is the same: measure, compare to target, adjust a digital setting, repeat.

Strengths and limitations

Strengths

• Very high speed relative to biological time, which suits studies of learning and plasticity.
• Low energy per synaptic event because the computation is physical.
• Flexible plasticity through an embedded processor with a general instruction set.
• A richer neuron model than the simplest integrate-and-fire neuron.
• Python interfaces for both neuroscience-style and machine-learning-style workflows.
• A compact chip that can serve as a layer inside hybrid models.
• Sensors for correlation allow learning rules that use local information.

Limitations

• Analog variability requires calibration, and results are not perfectly repeatable across chips.
• Few bits per weight limit precision.
• A single chip has a few hundred neurons, so large networks need multiple chips or time multiplexing.
• Speedup makes real-time interaction with the physical world hard.
• Communication between host and chip can limit throughput for large datasets.
• Noise and temperature sensitivity can affect circuits.
• Tooling and availability are research-grade.

Handling noise as a feature

Some research treats analog noise as a resource, not only a problem. Noise can act like a source of randomness for sampling-based inference, much like the roll of a die. Networks trained with noise included often become more robust to small variations, similar to how dropout makes a model tolerate missing inputs. Whether the noise helps or hurts depends on the task and on how well the training accounts for it.

How it compares with alternatives

Choosing between them

• If you need to explore slow plasticity quickly, BrainScaleS gives the highest acceleration.
• If you need deterministic, repeatable runs, a digital platform is safer.
• If you need a large network in real time with flexible models, SpiNNaker-like systems suit better.
• If you simply need efficient inference for a fixed model, a digital inference chip or a quantized edge accelerator may be simpler.

Software alternatives

For many projects, a GPU-based spiking library gives faster iteration than any hardware. Libraries such as snnTorch and SpikingJelly let you train and test spiking models on ordinary hardware. Hardware becomes interesting when energy, speed or on-device learning is the point of the project.

Role in tabular foundation models

Tabular foundation models learn from raw tables with rows, columns, mixed data types and missing cells. They are pre-trained on large sets of synthetic or real tables, and then use in-context learning: the labeled rows of a new table are given as context, and the model predicts without updating its weights. See /model/architecture, TabPFN and TabICL.

BrainScaleS cannot run such models. Their attention layers are dense and need high numeric precision, while BrainScaleS has a few hundred analog neurons and few-bit weights. The relationship is one of shared concepts and of possible small roles in research.

Concepts that connect

• Priors versus learning: a tabular foundation model learns a prior from many tables and applies it to a new one. BrainScaleS studies how fast local learning rules can build up structure from experience. Both ask how much to learn in advance and how much on the spot.
• Fast learning from few examples: in-context learning uses a handful of rows to adapt without weight updates. Plasticity experiments on the chip explore adapting with weight updates in very short wall-clock time. These are two answers to few-shot adaptation. See few-shot learning.
• Noise tolerance: analog noise forces models to be robust. Robustness training on tables, such as dropping cells at random, is a similar idea. See masked cell modeling and denoising autoencoders.
• Sampling: noisy analog neurons can draw samples from a distribution. Probabilistic prediction for tables, which gives uncertainty, can be seen as sampling too. See Bayesian deep learning.
• Quantization: few-bit weights are a hard constraint. Lessons from TurboQuant and mixed precision apply to getting models to survive coarse weights.

Possible research roles with table-like data

• Fast plasticity studies on feature streams: derived features from sensor tables can be encoded as spikes, and the chip can test learning rules quickly.
• Anomaly detection prototypes: a network learns normal input statistics and signals deviation, similar in aim to anomaly detection by reconstruction error.
• Continual learning experiments: because rules are programmable, one can test ways of avoiding forgetting at hardware speed. These tests relate to elastic weight consolidation, synaptic intelligence and experience replay, although the chip's local rules differ from loss-based methods.
• Imputation as pattern completion: recurrent networks can complete partial patterns. This relates conceptually to imputation networks.

Encoding table data for an analog chip

Because the chip is much faster than the world, the limit for tables is data movement, not computation. Sending a million rows to a chip that can process each in microseconds is limited by the link between host and chip. The analog part will wait.

Pre-training, synthetic data and semantics

Pre-training on large synthetic tables is a GPU-scale job, and nothing about BrainScaleS changes that. Sector or semantic classification of tables needs language understanding and large memory. A chip with hundreds of neurons cannot hold that. At best it could run a small classifier on features computed elsewhere.

Honest summary of the link

• BrainScaleS and tabular foundation models differ in scale, precision and purpose.
• The overlap lies in fast adaptation, robustness to noise and low-precision constraints.
• Claims that a tabular foundation model runs on this hardware should be treated with caution unless shown and measured.

See /model/benchmarks for how tabular models are evaluated on standard data.

Practical guidance and best practices

Decide whether the platform fits

• Do you need accelerated learning experiments?
• Is a small network adequate?
• Can you tolerate analog variability?
• Is the host link fast enough for your data?

Calibrate and recalibrate

• Run the full calibration before experiments.
• Store calibration data with results.
• Recalibrate when temperature or conditions change much.
• Check that key parameters, such as time constants and thresholds, match targets.

Train with the hardware in mind

• Use in-the-loop training so the real circuit is part of the forward pass.
• Quantize weights in software during training.
• Add noise in software to match the hardware spread.
• Keep a software reference to compare against.

Manage data movement

• Batch inputs to reduce overhead.
• Pre-compute features on the host.
• Keep the chip stage small and the host stages large.
• Measure time spent in transfer separately from emulation time.

Handle repeatability

• Expect small differences between runs and between chips.
• Report averages over trials and chips.
• Keep seeds and settings.

Start simple

• Reproduce a small published experiment before building your own.
• Test one neuron, then one layer, then the network.
• Check that single-circuit behavior matches the model.

A typical experiment, end to end

A first project on an accelerated analog system tends to follow the same arc. The list below shows it in plain terms.

1. Write the experiment on paper first. Name the neuron count, the connections, the input pattern and the quantity you want to measure.
2. Express the network in the high-level software interface, so that it is independent of the chip.
3. Check that the network fits the physical limits: neuron count, fan-in per neuron and available synapse rows.
4. Run calibration so that the neurons behave close to the parameters you asked for.
5. Run a short test with a single input to see that spikes appear at all.
6. Run the full experiment many times, because analog noise means each run differs a little.
7. Compare the results with a software simulation of the same network, and write down the gap.
8. Adjust the training or the parameters to narrow the gap, and repeat.

The key habit is step 7. A software reference is the ruler against which the hardware is judged. Without it, a result cannot be interpreted.

Translating between biological and hardware units

Because the hardware runs on its own time scale, every number in a paper needs a unit conversion. People often keep two columns in their notes: the value in model time and the value in wall-clock time.

The exact speed-up factor depends on the generation and on the configuration, so always read it from the documentation of the system you use instead of assuming it.

A kitchen analogy for calibration

Imagine a row of ovens that all claim to run at 180 degrees. In practice one runs hot, one runs cool and one drifts during the day. A careful cook places a thermometer in each oven and writes down the offset. Calibration on an analog chip is the same job. Every neuron circuit is a slightly different oven, and the software measures each one and sets a correction so that the dish comes out the same everywhere. Because the weather (temperature) changes, the cook checks again from time to time.

Questions to ask before choosing a neuromorphic platform

• Do I need fast experiments with plasticity, or low-power inference at the edge?
• Is my network small enough for the physical neuron and synapse counts?
• Can my task tolerate few-bit weights and some noise?
• Do I need exact repeatability, or is a statistical match to a simulation enough?
• Is access to the system possible for my team, for example through a research program or a shared service?
• Would a digital neuromorphic chip, a GPU simulator or plain PyTorch do the job at lower risk?

If the answers point to a general machine learning job, a software spiking library such as snnTorch, Norse or SpikingJelly is usually the more practical start.

Sources of mismatch between hardware and simulation

Why spikes and not numbers

A conventional neural network sends real numbers between layers. A spiking network sends short events in time. The difference is like the one between a thermometer that shows a continuous reading and a doorbell that rings. Information is carried by when and how often the bell rings. This is cheap in hardware, because silence costs almost nothing. It is also hard to train, because the bell is all or nothing and has no smooth slope. That is why surrogate gradients and local learning rules matter so much in this field.

Learning rules that fit the hardware

• Spike-timing-dependent plasticity strengthens a connection when the sender fires just before the receiver and weakens it in the opposite case.
• Reward-modulated variants multiply that change by a global signal, so that useful behavior is reinforced.
• Homeostatic rules keep the average firing rate near a target so that no neuron falls silent or runs away.
• Gradient-style rules approximate backpropagation by using surrogate derivatives computed on the plasticity processor or on a host.

Because the plasticity processor is programmable, a research group can try a new rule by changing a small program instead of fabricating a new chip.

Reading the literature

When reading a paper on neuromorphic hardware, check the following points. They quickly separate solid work from loose claims.

• Is the speed or energy figure measured for the whole system or only for the chip core?
• Is the accuracy figure reported on the hardware or only in simulation?
• How many runs were averaged, and is the spread shown?
• What was the weight precision during inference?
• Was calibration repeated, and how often?
• Is the task a standard benchmark or a custom toy problem?

A short list of project ideas that stay honest

• Reproduce a small spiking classifier on the hardware and compare its accuracy with the software version.
• Study how accuracy falls as weight precision is reduced from many bits to few bits.
• Measure how much noise a rate-coded readout can absorb before accuracy drops.
• Test a local plasticity rule on a toy association task.
• Build a tiny pattern-completion network and measure how many missing inputs it can survive.

More notes on tabular thinking with spiking systems

A table has rows, columns, mixed types and gaps. A spiking chip has neurons, synapses and events. Bridging them needs a deliberate encoding step. Numeric columns can be turned into rates or into the position of a bump in a population of neurons. Categories can become one-hot spike channels. A missing value can be represented by silence on that channel, which is a natural fit, because silence costs nothing. Whether that representation is good is an empirical question, and for most real tables a tree model or a tabular foundation model will win on accuracy by a wide margin. The value of the analog route lies in research on efficiency and robustness, not in leaderboard results. See /model/benchmarks for how tabular methods are actually compared.

Common mistakes

• Skipping calibration and blaming the model.
• Training only in software and deploying without hardware-in-the-loop correction.
• Using weights with too much precision for the synapse circuits.
• Ignoring the host link as the bottleneck.
• Expecting real-time interaction at a thousand-fold speedup.
• Comparing with a digital platform without accounting for variability.
• Using a chip for tasks that need large networks without a plan for multiplexing.
• Failing to record calibration and temperature with the results.
• Treating the noise as pure error when the task might exploit it.
• Overlooking that a software spiking library might solve the problem faster.

Additional pitfalls

• Treating a single successful run as proof, when analog noise means results must be averaged.
• Forgetting to log the calibration date and chip temperature next to each result.
• Comparing hardware speed with software speed without counting setup and data transfer.

Frequently asked questions

What is BrainScaleS?

BrainScaleS is a neuromorphic computing system that emulates spiking neurons with analog electronic circuits. It runs much faster than biological time and includes digital parts for communication and for plasticity, which makes it a platform for studying fast learning in spiking networks.

What does BrainScaleS stand for?

It stands for Brain-inspired multiscale computation in neuromorphic hybrid systems. The name reflects both the brain inspiration and the mix of analog and digital technology.

How fast is BrainScaleS?

The first generation ran about ten thousand times faster than biological time, and the second generation runs about a thousand times faster. A process that takes one second in biology takes about a millisecond on the second-generation chip.

Why use analog circuits for neurons?

Analog circuits let the physics of transistors and capacitors mimic the neuron equation directly. This uses little energy and can be very fast. The trade-off is variability between circuits, which needs calibration and careful training.

What is the plasticity processing unit?

It is an embedded processor on the second-generation chip with vector instructions. It reads correlation sensors and other signals and then updates synaptic weights and neuron parameters, which allows a wide range of learning rules to be implemented in software.

How is BrainScaleS programmed?

Researchers use Python interfaces. A PyNN-style interface serves neuroscience models, and a PyTorch-based interface lets the chip act as a layer in a machine learning model. Low-level tools exist for direct control of the hardware.

What is in-the-loop training?

In-the-loop training runs the forward pass on the real chip and computes weight updates on a host with the help of a software model for the gradient. This lets the training account for the chip's imperfections instead of assuming an ideal circuit.

Can BrainScaleS run tabular data?

Table values can be converted to spikes and presented to the chip, and small networks can be trained on derived features. It is a research platform, and it does not run tabular foundation models, which use dense attention and higher precision.

How does BrainScaleS differ from Loihi and SpiNNaker?

BrainScaleS is analog and accelerated, so it is fast and efficient but variable. Loihi is digital with on-chip learning and deterministic behavior. SpiNNaker runs neuron models as software on many cores in real time, which is flexible but less efficient.

Is BrainScaleS available to use?

Access has been offered to researchers through a cloud-style service and collaborations. Availability and terms change, so check with the project before planning work around it.

Glossary

• Adaptive exponential integrate-and-fire: A neuron model with an exponential spike-onset term and an adaptation variable.
• Analog circuit: A circuit whose voltages and currents vary continuously.
• Calibration: Adjusting digital settings so that analog circuits reach target behavior.
• Correlation sensor: A synapse-level circuit that records how pre- and post-synaptic spikes line up in time.
• Emulation: Running a model on a physical system whose behavior mirrors the model.
• Fixed-pattern noise: Stable differences between circuits caused by manufacturing.
• Hybrid plasticity: Combining analog sensing with a digital processor that applies learning rules.
• In-the-loop training: Training with the real hardware included in the forward pass.
• Mixed-signal: Containing both analog and digital circuits.
• Plasticity processing unit: The embedded processor that updates weights and parameters.
• Speedup factor: How many times faster the hardware runs than biological time.
• Spike: A short event emitted when a neuron voltage crosses a threshold.
• Synapse circuit: A circuit that holds a weight and passes current into a neuron.
• Wafer-scale integration: Using an entire wafer as a single system.

Summary

BrainScaleS is a mixed-signal neuromorphic system that emulates spiking neurons with analog circuits running hundreds to thousands of times faster than biological time. Its second generation adds a plasticity processor that supports flexible learning rules, and it offers Python and PyTorch-style interfaces. Its strengths are speed, low energy and fast plasticity experiments, while its limits are analog variability, few-bit weights and small network size.

For tabular foundation models, BrainScaleS is a neighbor, not a host. The overlap lies in few-shot adaptation, robustness to noise, low-precision weights and probabilistic sampling, and small prototypes of anomaly detection or pattern completion can be explored on derived features. Continue with Intel Loihi, SpiNNaker, IBM TrueNorth and /model/architecture.

Related

It belongs to Neuromorphic in my stack, under AI and machine learning. Others in the same group: