Intel Loihi

Overview

Intel Loihi is a family of research chips for neuromorphic computing. Instead of multiplying large dense matrices every clock tick, a Loihi chip simulates many small artificial neurons that send short messages, called spikes, to each other. A neuron does work only when a spike arrives. This event-driven style can save a great deal of energy when the input is sparse, such as a sensor that changes only now and then.

Loihi is aimed at researchers who study spiking neural networks, sparse coding, on-chip learning and low-power inference at the edge. It is not a general replacement for a GPU. Large dense models, including today's tabular foundation models, still run best on conventional accelerators. Loihi matters for tabular work mainly in streaming and edge cases: detecting unusual events in sensor tables, learning continually on a device, and exploring how sparse, spike-based computation could one day carry some of the load. See spiking neural networks for the model class that Loihi runs.

What it is

Loihi is a digital, asynchronous, many-core processor built around a mesh of neuromorphic cores. Each core holds a group of neurons and the synapses that connect them. Cores talk to each other by sending spike messages over an on-chip network. Small embedded processors on the chip handle setup, input and output, and some learning rules.

The building blocks

• Neuron: a small unit with a state (a voltage-like number) that rises when input arrives and decays over time. When the state passes a threshold, the neuron fires a spike and resets.
• Synapse: a weighted connection from one neuron to another. A spike passing through a synapse adds its weight to the target neuron.
• Core: a block that stores the state of many neurons and a table of their synapses, and updates them.
• Mesh: the network that routes spikes between cores.
• Learning engine: hardware that can change synaptic weights based on spike timing, so the chip can learn while it runs.

Analogy: picture a large office where each worker sits idle until a note is placed on the desk. A worker who gets enough notes writes a note to a few colleagues. If nobody sends notes, the office is silent and uses almost no power. A normal processor is more like an office where every worker does a calculation on every tick, whether or not anything changed.

Generations

• First generation (Loihi): introduced in 2017 and described publicly in 2018. It was made in a 14 nanometer process and held on the order of one hundred thousand neurons and over one hundred million synapses on one chip, spread over 128 cores.
• Second generation (Loihi 2): announced in 2021, built in a newer process. It offers more neurons per chip, faster operation, more flexible neuron models that can be programmed, richer spike messages that carry integer values, and better support for scaling across many chips.
• Systems: Intel has built boards and multi-chip systems for researchers, from small USB-sized units for edge experiments to rack-scale systems with hundreds or over a thousand chips and a neuron count in the billions.

Exact figures vary by source and version, so treat the numbers above as orders of magnitude.

What it is not

• It is not a drop-in accelerator for standard deep learning frameworks. Models must be mapped to spiking form.
• It is not an analog chip. Its circuits are digital, which makes behavior repeatable.
• It is not a consumer product. It is offered to a research community.
• It is not a brain simulator in the biological sense. It borrows ideas, not details.

Where it came from

Neuromorphic engineering began in the late 1980s, when researchers proposed building circuits that mimic nerve cells using the physics of transistors. The idea was that brains compute with tiny energy budgets, and that hardware designed around the same principles might do the same.

Several milestones shaped the field:

• Early analog silicon neurons and retinas in the 1990s.
• Large government-funded programs in the 2000s and early 2010s that produced the first multi-core neuromorphic chips. IBM TrueNorth is a well-known result from that era.
• Large-scale European projects that produced SpiNNaker and BrainScaleS.
• A shift to chips with on-chip learning, which is where Loihi positioned itself.

Loihi was introduced by Intel Labs. A 2018 paper in IEEE Micro, titled "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning", described the first chip. It explained the neuron model, the mesh, the learning engine and the programming approach. Later work focused on the second generation and on an open-source software framework called Lava, which lets developers describe processes and connect them, and run them on a CPU, on Loihi, or on other targets.

Research results published by the community include sparse coding, nearest-neighbor search, constraint satisfaction, graph search, olfactory-style recognition, robot control and keyword spotting. Some reported large energy savings against conventional hardware on those tasks. Claims depend heavily on the task and the baseline, so it is wise to read each study closely.

For the wider context of model research on this site, see /model/research.

How it works

Step 1: represent information as spikes

Data must be turned into spike trains. There are several common ways:

• Rate coding: a larger value means more spikes per time window.
• Temporal coding: a larger value means an earlier spike.
• Population coding: a value activates a bump of neurons around a preferred value, like a set of overlapping thermometers.
• Delta coding: a spike is sent only when a value changes by more than a threshold, which suits sensors.

Analogy: a spike train is like a Morse code message. The pattern in time carries the meaning, not a big block of numbers.

Step 2: neurons integrate and fire

The standard neuron model on Loihi is a leaky integrate-and-fire type. Each neuron has a current and a voltage. Input spikes add to the current. The current feeds the voltage. Both decay over time by set factors. When the voltage crosses a threshold, a spike goes out and the voltage resets.

A bathtub is a fair picture. Water pours in (input spikes). A small hole lets water leak out (decay). If the water level reaches the overflow line (threshold), the tub tips and sends a pulse, then refills from empty.

Step 3: spikes travel through the mesh

Spikes are routed as small packets. Only active neurons generate traffic. A core does work when it receives a packet, and goes quiet otherwise. This is the source of the energy savings on sparse data.

Step 4: time advances in discrete steps

Though the hardware is asynchronous within a step, the computation is organized into algorithmic time steps. In each step, the cores finish their updates, and a barrier makes sure all spikes of that step are delivered before the next begins. This gives deterministic, repeatable results.

Step 5: learning rules adjust weights

The learning engine can change synaptic weights using local rules, such as spike-timing-dependent plasticity. The rule uses the timing of spikes before and after a synapse. If the sending neuron fires just before the receiving neuron, the connection is strengthened. If the order is reversed, it is weakened.

Analogy: two friends who often arrive at the party together become a pair in people's minds. Two who never arrive together are forgotten as a pair.

On Loihi 2, learning rules are more programmable, so a developer can write custom update rules.

Step 6: read out results

Output can be read from spike counts, from the time of first spike, or from membrane values read by the embedded processors. The host computer then collects the answer.

Two ways to get a model onto the chip

1. Train a spiking network directly, using surrogate gradients or local plasticity, then deploy it.
2. Convert a trained conventional network, where each activation value becomes a firing rate. This is simple but can need many time steps and loses some accuracy.

Libraries such as snnTorch and SpikingJelly are used to train spiking networks on regular GPUs. The trained weights can then be mapped to neuromorphic hardware through vendor tools. Check the current toolchain for supported neuron models and weight precision.

Why sparsity matters

If a network has ten percent of neurons active at any moment, an event-driven chip does about ten percent of the work. A dense processor does all of it, since it cannot know in advance which values are zero. The more sparse the activity, the bigger the gap. When activity is dense, the advantage shrinks or disappears.

Typical research workloads

• Keyword spotting and gesture recognition: small networks listen to a stream and fire only when a pattern appears.
• Optimization: constraint satisfaction, graph coloring and shortest-path problems can be mapped so that the network settles into a valid answer.
• Robot control: a compact network turns sensor events into motor commands with tight latency.
• Olfactory-style recognition: a few examples are enough to learn a new pattern, which hints at fast, local learning.
• Sparse coding: a layer finds a small set of active units that explains the input, much like picking a few ingredients that rebuild a dish.
• Similarity search: stored patterns compete to match a new input, which is close to how a nearest-neighbor lookup works.

Memory and data movement

In a conventional computer, the processor and the memory sit far apart, and moving numbers back and forth costs more energy than adding them. Loihi keeps each neuron's state and its synapses inside the same core. Analogy: a cook who has the ingredients on the counter works faster and walks less than a cook who fetches each item from a warehouse across town. This idea, sometimes called in-memory or near-memory computing, is a large part of the energy story.

Scaling across chips

Chips can be linked so that spikes cross chip boundaries over off-chip links. The software hides much of the routing, but a network that crosses many chips pays latency for each hop. Good partitioning keeps strongly connected neurons on the same core, then on the same chip. This resembles placing people who talk a lot in the same room.

Key concepts and terms

A worked example

We will walk through a single leaky integrate-and-fire neuron by hand, then write a small simulation. This is the same dynamic the chip runs in hardware, in a simplified form. We will then show how a table row could be turned into spikes.

Hand calculation

Parameters:

• Voltage decay factor per step: 0.9 (the voltage keeps 90 percent each step).
• Threshold: 1.0.
• Input weight: 0.4 per incoming spike.

Input spikes arrive at steps 1, 2, 3 and 6.

Three close spikes make the neuron fire. A lone spike at step 6 does not. This is the neuron acting as a coincidence detector.

Simulation in Python

import numpy as np

def lif(spike_inputs, weight=0.4, decay=0.9, threshold=1.0):
    v = 0.0
    out = []
    for s in spike_inputs:
        v = decay * v + weight * s
        if v >= threshold:
            out.append(1)
            v = 0.0
        else:
            out.append(0)
    return out

inputs = [1, 1, 1, 0, 0, 1]
print(lif(inputs))   # expected: [0, 0, 1, 0, 0, 0]

Encoding a table row as spikes

Take a numeric row with three columns: temperature, pressure and vibration. Scale each column to the range 0 to 1 using the training data. Then use rate coding over 20 time steps.

rng = np.random.default_rng(0)

def rate_encode(x, steps=20):
    # x in [0, 1]; probability of a spike each step equals x
    return (rng.random(steps) < x).astype(int)

row = np.array([0.80, 0.10, 0.55])
spikes = np.stack([rate_encode(v) for v in row])
print(spikes.sum(axis=1))   # roughly [16, 2, 11]

The second column is quiet, so it generates few events. On event-driven hardware, quiet columns cost little.

Delta encoding for a sensor stream

For streams, send an event only when a value changes by more than a margin:

def delta_encode(series, margin=0.05):
    events, last = [], series[0]
    for t, x in enumerate(series[1:], start=1):
        if abs(x - last) > margin:
            events.append((t, +1 if x > last else -1))
            last = x
    return events

print(delta_encode([0.50, 0.51, 0.52, 0.60, 0.61, 0.40]))

A slowly drifting sensor makes no events. A sudden jump creates one. This fits the event-driven model well, and it is the basis of many low-power anomaly detectors.

From simulation to hardware

In a real project, the same network would be written in a framework such as Lava, tested first on a CPU simulation, and then run on a Loihi board. A rough project flow is:

1. Prototype the spiking model in Python and measure accuracy.
2. Quantize weights to the precision the chip supports.
3. Map the network to cores and check that it fits memory limits.
4. Run on hardware and compare outputs with the simulation.
5. Measure energy and latency for the true workload, not a toy one.

Variations worth trying

1. Change the decay to 0.5 and rerun the hand example. Notice that the neuron now needs a much denser burst to fire, because the voltage leaks away faster.
2. Raise the weight to 0.6. Two spikes in a row now suffice. Weight and threshold trade off against each other.
3. Add a refractory period of two steps after each spike. The neuron then cannot fire at the maximum rate, which stabilizes the network.
4. Replace the fixed weight with a learned one, and apply a simple timing rule: raise the weight a little when the input spike precedes an output spike.

A tiny anomaly detector sketch

The idea is to learn what normal looks like and to fire when something else arrives.

def detect(events, window=5, limit=3):
    # count events in a sliding window; fire when too many arrive
    alerts = []
    for t in range(len(events)):
        lo = max(0, t - window + 1)
        if sum(e for e in events[lo:t + 1]) >= limit:
            alerts.append(t)
    return alerts

stream = [0, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0]
print(detect(stream))

On a neuromorphic chip, the same behavior comes from one neuron with a leak and a threshold, which is cheaper than storing a window of counts. The example shows why event-driven detectors can be so small.

Strengths and limitations

Strengths

• Very low energy for sparse, event-like workloads.
• Low latency for streaming input, since there is no need to batch.
• On-chip learning allows adaptation without a round trip to a server.
• Deterministic digital behavior makes experiments repeatable.
• Scalable: many chips can be connected to form larger systems.
• Good fit for constraint problems, graph search and sparse coding, which have been shown in research.
• Active open-source software and an academic community.

Limitations

• Mapping standard deep learning models is difficult and often loses accuracy.
• Training spiking networks is harder than training ordinary ones. Gradients do not pass through the spike step directly.
• Memory per core is limited, which restricts network size per chip.
• Dense workloads, such as large matrix multiplications, do not benefit.
• Access is mainly through research programs, not general purchase.
• The software stack is younger than mainstream tools. Debugging is less convenient.
• Benchmarks are task-specific, and comparisons with GPUs depend on batch size, precision and how sparse the data is.
• Floating-point style numeric range is limited, which complicates models that depend on precise values.

Where energy claims need care

An energy figure is only meaningful with a baseline. Ask these questions about any claim:

• Was the baseline a GPU at full utilization, or one running a batch of one?
• Was the input naturally sparse, or was it made sparse?
• Does the figure include data transfer to and from the host?
• Was accuracy equal on both sides?
• Was the model the same size?

How it compares with alternatives

Choosing among them

• If you need to run existing dense models, use a GPU or an edge NPU.
• If you want to study on-chip learning and sparse event processing with repeatable digital behavior, Loihi is a natural choice.
• If you want to simulate big spiking networks in real time with flexible models, SpiNNaker-style machines suit that goal.
• If you want fast analog emulation and learning experiments, BrainScaleS suits that goal.

Role in tabular foundation models

Tabular foundation models learn from raw tables, which have rows, columns, mixed types and missing cells. They are pre-trained on large collections of synthetic or real tables, then applied to a new table through in-context learning: the training rows are given as context and the model predicts without weight updates. See /model/architecture for how such a model is organized, and TabPFN and TabICL for well-known examples.

Loihi is not where those models run today. They depend on attention over many rows and columns, which means large dense matrix operations. That is the workload neuromorphic chips are weakest at. Still, there are honest and concrete links.

Where Loihi could touch tabular data

• Streaming tables: sensor logs, transaction streams and machine telemetry are tables that grow one row at a time. Event-driven chips handle such streams without batching.
• Edge anomaly detection: a small spiking network can watch a few columns on a device and flag unusual rows at very low power. This is a counterpart to anomaly detection methods such as isolation forest, running at the edge.
• Continual learning: on-chip plasticity lets a device keep adapting to drift in its own data. This is related to the goals of elastic weight consolidation and experience replay, but the mechanisms are local synaptic rules rather than loss penalties or stored samples.
• Sparse coding and nearest-neighbor search: matching a new row to stored rows is the heart of in-context tabular prediction. Neuromorphic nearest-neighbor demonstrations show that similarity search can be done in a spike-based way.
• Sparsity: tables with many zeros or missing cells have sparse structure that event-driven hardware can exploit, if rows are encoded as events.

Encoding challenges for tables

• Mixed types: numbers can be rate- or population-coded. Categories can be one-hot (one neuron per level) or hashed. Text and dates need extra steps.
• Missing values: in a spike code, a missing value can simply be silence, but silence is also a valid value of zero. A separate "missing" neuron avoids this confusion.
• No column names: spike encoding of anonymous columns works by position or by learned input weights, so names are not required. Column meaning must come from the data.
• Scale: every numeric column needs normalization before it can be turned into a rate or a population code.
• Precision: rate codes need many time steps for fine accuracy, which cuts into the energy advantage.

Mapping table concepts to spike concepts

The table shows that nothing about a table is impossible to encode. The cost is in width, precision and time steps. This is why compact, low-dimensional streams suit the chip, and wide tables with hundreds of columns do not.

Imputation and anomaly detection

A spiking autoencoder could, in principle, predict a missing cell from the others and flag surprising rows by reconstruction error. Related research on dense models is discussed under imputation networks. Demonstrations of this on neuromorphic hardware are small. Today, treat it as an experimental direction rather than a product path.

Pre-training on synthetic tables

Pre-training with synthetic data is done on GPUs at large scale. A spiking model for tables could in principle be pre-trained the same way and then converted, but conversion of attention-based models is an open research problem. A more realistic near-term path is to distill the decisions of a large model into a small spiking or sparse model for the edge.

Sector and semantic classification

Classifying what a table is about, such as its industry or sector, relies on semantic understanding of column content and values. That calls for language-aware components that are far larger than anything a current neuromorphic chip holds. A neuromorphic device might still run a compact classifier on pre-computed features at the edge.

Honest summary of the link

• Loihi and tabular foundation models target different regimes: sparse, streaming, tiny-power versus dense, batch, large-scale.
• The meeting point is the edge: small, adaptive, event-driven models that watch tabular streams.
• Claims of direct integration should be treated with caution unless they are demonstrated and measured.

For how tabular models are evaluated on standard datasets, see /model/benchmarks.

Practical guidance and best practices

Decide whether neuromorphic is the right tool

• Is the input naturally event-based or sparse?
• Is power or latency the binding constraint?
• Does the task benefit from learning on the device?
• Is a small network enough?

If most answers are no, a standard accelerator is simpler.

Start in simulation

• Build and train the model with a spiking library on a CPU or GPU first.
• Use the open-source Lava framework to describe the process graph and test it on a CPU backend.
• Measure accuracy before thinking about hardware.

Design the encoding first

• Spend more time on how the data becomes spikes than on the network. Encoding often decides the outcome.
• Use delta coding for slowly changing signals.
• Use population coding for numbers that need resolution.
• Keep the time window short to save energy and latency.

Respect hardware limits

• Check the maximum neurons and synapses per core.
• Check supported weight precision and fan-in limits.
• Plan for the cost of moving data between the host and the chip.
• Use quantization-aware training so that the deployed network matches the trained one.

Measure honestly

• Compare against a well-tuned baseline on the same task.
• Report accuracy, latency and energy together.
• Include the cost of encoding and host communication.
• Use realistic input rates.

Think about learning on the device

• Local rules are limited in what they can learn. They suit adaptation and fine-tuning better than learning from scratch.
• Guard against forgetting by limiting the learning rate or by freezing parts of the network.
• Log weight statistics to detect drift.

Budget thinking

Before choosing hardware, write down three numbers: how many events per second arrive, how quickly a decision is needed, and how much power is allowed. If events are rare, latency is tight and power is small, a neuromorphic design is worth a pilot. If events are constant, latency is relaxed and power is plentiful, a standard processor wins on simplicity.

Team and tooling

• Pair someone who knows spiking models with someone who knows the data.
• Keep a regular CPU reference model so that results can be compared at each stage.
• Version the encoding code with the model, because they are one system.
• Plan for small, repeatable experiments rather than one large run.

Common mistakes

• Assuming spiking means automatically efficient. Dense activity removes the advantage.
• Converting a large conventional network without checking accuracy loss.
• Choosing a rate code with too few time steps, which adds noise.
• Ignoring data movement costs between the host and the chip.
• Comparing against a poorly tuned or underused GPU baseline.
• Treating silence as zero when missing values exist.
• Skipping normalization of numeric columns before encoding.
• Planning around production availability when the platform is a research offering.
• Expecting a neuromorphic chip to run attention-heavy models.
• Overlooking that learning rules on chip are local and may not match gradient-trained results.

Frequently asked questions

What is Intel Loihi used for?

Loihi is used mostly for research. Typical topics include low-power sensing, sparse coding, nearest-neighbor search, optimization problems, robot control and on-chip learning. It lets researchers test how event-driven spiking networks behave on dedicated hardware instead of on a simulation.

Is Loihi a GPU or an AI accelerator?

It is a different kind of processor. A GPU performs dense math on large blocks of numbers. Loihi simulates spiking neurons that communicate by events, and does work only when events occur. It is an accelerator for a specific style of computation, not a general deep learning engine.

What is the difference between Loihi and Loihi 2?

Loihi 2 is the second generation. It offers more neurons per chip, faster operation, more programmable neuron models and learning rules, spikes that can carry integer values, and better support for scaling across chips. The core idea of event-driven spiking computation stays the same.

How is Loihi programmed?

Developers describe networks as connected processes, often with the open-source Lava framework in Python. They can test the design on a CPU, then run it on Loihi hardware. Spiking networks can also be trained with other libraries and mapped to the chip.

Can Loihi run a transformer or a tabular foundation model?

Not in a practical way today. Transformers rely on dense attention and large matrix operations, which suit GPUs. Research on spiking versions of attention exists, but running a full tabular foundation model on Loihi is not a realistic deployment path at this time.

Why is Loihi energy efficient?

It computes only when a spike arrives, and it keeps memory next to the compute units, which limits data movement. If the workload is sparse, most neurons stay idle and consume little. The savings shrink when activity is dense or when the host and encoding costs dominate.

Does Loihi support learning?

Yes. It has a learning engine that can change synaptic weights using local rules based on spike timing and other signals. Loihi 2 makes these rules more flexible. This is different from backpropagation, so it suits adaptation and certain unsupervised tasks better than large supervised training.

How do you feed tabular data to a spiking network?

You encode each value as spikes. Numbers can use rate, temporal or population codes, and streams can use delta codes. Categories can be one-hot. A separate input can signal a missing value. The quality of this encoding strongly affects results.

Is Loihi available to buy?

It is offered mainly through research programs and partnerships rather than as a general consumer product. Availability and terms change, so check current information from the vendor before planning a project around it.

How does Loihi relate to other neuromorphic chips?

It belongs to the same family as TrueNorth, SpiNNaker and BrainScaleS. Each takes a different design path: digital with on-chip learning, digital with fixed neurons, many general-purpose cores, or analog circuits. See the sibling pages for details on each.

Glossary

• Asynchronous: Not driven by a single global clock; parts run when they have work.
• Delta coding: Sending an event only when a value changes by more than a margin.
• Edge computing: Running models on or near the device that produces the data.
• Event-driven: Computing only in response to input events.
• Graded spike: A spike that carries a small integer value along with the event.
• Lava: An open-source software framework for building neuromorphic applications.
• Leaky integrate-and-fire: A simple neuron model that accumulates input, leaks over time and fires at a threshold.
• Neuromorphic: Designed with ideas taken from biological nervous systems.
• Plasticity: The ability of connection strengths to change with activity.
• Population coding: Representing a value by the activity of a group of neurons.
• Rate coding: Representing a value by the number of spikes in a time window.
• Spike: A short event emitted by a neuron when its state passes a threshold.
• Spiking neural network: A neural network that computes with spikes in time.
• STDP: Spike-timing-dependent plasticity, a learning rule that depends on spike order.
• Surrogate gradient: A smooth approximation used to train networks through the non-differentiable spike.
• Synapse: A weighted connection between two neurons.

Summary

Intel Loihi is a neuromorphic research processor that runs spiking neural networks with event-driven, low-power computation and on-chip learning. It shines on sparse, streaming and adaptive workloads, and it is held back by limited memory per core, a younger software stack and the difficulty of training or converting spiking models.

For tabular foundation models, which depend on dense attention over rows and columns, Loihi is not a deployment target. Its relevance is at the edge: encoding table rows and sensor streams as spikes, detecting anomalies at low power, and adapting continually on a device. Read on about spiking neural networks, SpiNNaker, BrainScaleS and /model/architecture.

Related

It belongs to Neuromorphic in my stack, under AI and machine learning. Others in the same group: